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IS24C32A/B IS24C64A/B
65,536 bit/32,768 bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
* Two-Wire Serial Interface -Bi-directional data transfer protocol * 400 KHz (I2C Protocol) Compatibility * Low Power CMOS Technology -Standby Current less than 6 A (5.0V) -Read Current less than 2 mA (5.0V) -Write Current less than 3 mA (5.0V) * Flexible Voltage Operation -Vcc = 1.8V to 5.5V for -2 version -Vcc = 2.5V to 5.5V for -3 version * Hardware Data Protection -IS24C32A/64A: WP protects entire array -IS24C32B/64B: WP protects top quarter of array * Sequential Read Feature * Filtered Inputs for Noise Suppression * 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP packages * Self time write cycle with auto clear 5 ms @ 2.5V * Organization: -IS24C32A/B: 4Kx8 (128 pages of 32 bytes) -IS24C64A/B: 8Kx8 (256 pages of 32 bytes) * 32 Byte Page Write Buffer * High Reliability -Endurance: 1,000,000 Cycles -Data Retention: 100 Years * Commercial and Industrial temperature ranges
ISSI
ADVANCED INFORMATION MAY 2004
(R)
DESCRIPTION
The IS24C32A/B and IS24C64A/B are electrically erasable PROM devices that use the standard 2wire interface for communications. The IS24C32A/B and IS24C64A/B contain a memory array of 32Kbits (4K x 8) and 64K-bits (8K x 8), respectively. Each device is organized into 32 byte pages for page write mode. This EEPROM is offered in wide operating voltages of 1.8V to 5.5V (IS24Cxx-2) and 2.5V to 5.5V (IS24Cxx-3) to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are available in 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP packages. The IS24C32A/32B/64A/64B (IS24CXX) maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24CXX has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.
Copyright (c) 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
1
IS24C32A/B IS24C64A/B
FUNCTIONAL BLOCK DIAGRAM
ISSI
HIGH VOLTAGE GENERATOR, TIMING & CONTROL
(R)
Vcc
8
SDA SCL WP
5
7
X DECODER
6
CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR
EEPROM ARRAY
A0 A1 A2
1 2 3
WORD ADDRESS COUNTER
Y DECODER
GND
4
ACK
Clock DI/O
>
nMOS
DATA REGISTER
PIN DESCRIPTIONS
A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground
PIN CONFIGURATION 8-Pin DIP, SOIC, and TSSOP
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
SCL
This input clock pin is used to synchronize the data transfer to and from the device.
WP
WP is the Write Protect pin. The input level determines if all, partial, or none of the array is protected from modifications. Write Protection Array Addresses Protected
WP GND or floating Vcc IS24C32A/64A None Entire Array IS24C32B None C00h -FFFh IS24C64B None 1800h -1FFFh
SDA
The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the 24C16. When pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system. When the pins are not hardwired, the default values of A0, A1, and A2 are zero.
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
IS24C32A/B IS24C64A/B
ISSI
Stop Condition
(R)
DEVICE OPERATION
IS24CXX features serial communication and supports a bidirectional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by a Master device that generates the SCL, controls the bus access, and generates the Stop and Start conditions. The IS24CXX is the Slave device on the bus.
The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line.
Reset
The IS24CXX contains a reset function in case the 2wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line, which may cycle the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.)
The Bus Protocol:
- Data transfer may be initiated only when the bus is not busy - During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. The state of the data line represents valid data after a Start condition. The data line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition.
Standby Mode
Power consumption is reduced in standby mode. The IS24CXX will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if a no write operation is initiated; or c) Following any internal write operation.
Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
3
IS24C32A/B IS24C64A/B
DEVICE ADDRESSING
The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave (Fig. 5) address is 8 bits. The four most significant bits of the address are fixed as 1010 for the IS24CXX. The next three bits of the Slave address are A0, A1, and A2, and are used in comparison with the hard-wired input values on the A0, A1, and A2 pins. Up to eight IS24CXX units may share the 2-wire bus. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg.IS24C64A) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus.
ISSI
WRITE OPERATION Byte Write
(R)
In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the two byte address that is to be written into the address pointer of the IS24CXX. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.
Page Write
The IS24CXX is capable of 32-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 31 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 32 bytes prior to issuing the Stop condition, the address counter will "roll over," and the previously written data will be overwritten. Once all 32 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24CXX initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the IS24CXX has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation.
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
IS24C32A/B IS24C64A/B
READ OPERATION
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to "1". There are three Read operation options: current address read, random address read and sequential read.
ISSI
Random Address Read
(R)
Current Address Read
The IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to "1"), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.)
Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the IS24CXX acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the IS24CXX. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1, n+2 ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of 8191 for IS24C64A/B or 4095 for IS24C32A/B (depending on the device) is reached, the address counter "rolls over" to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
5
IS24C32A/B IS24C64A/B
Figure 1. Typical System Bus Configuration
Vcc
ISSI
SDA SCL
Master Transmitter/ Receiver
(R)
IS24CXX
Figure 2. Output Acknowledge
SCL from Master
1
8
9
Data Output from Transmitter
tAA tAA
Data Output from Receiver
ACK
Figure 3. START and STOP Conditions
STOP Condition
SDA
START Condition
SCL
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
IS24C32A/B IS24C64A/B
Figure 4. Data Validity Protocol
ISSI
Data Change
(R)
SCL
Data Stable Data Stable
SDA
Figure 5. Slave Address
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 6. Byte Write
S T A R T W R I T E S T O P A C K
Device Address
SDA Bus Activity
M S B
Word Address Word Address A A A C***# C C K K K L M S * = Don't care bits S B B # = Don't care bit for 24C32A/B R/W
Data
Figure 7. Page Write
S T A R T W R I T E S T O P A C K
Device Address
SDA Bus Activity
Word Address (n) Word Address (n) A A A C C***# C K K K * = Don't care bits # = Don't care bit for 24C32A/B
Data (n) A C K
Data (n+1) A C K
Data (n+31)
M S B
L S B R/W
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
7
IS24C32A/B IS24C64A/B
Figure 8. Current Address Read
S T A R T SDA Bus Activity M S B L S B R/W
ISSI
Device Address R E A D A C K N O A C K S T O P
(R)
Data
Figure 9. Random Address Read
S T A R T SDA Bus Activity M S B W R I T E S T A R T A C K
Device Address
Word Address (n) A C* * *# K A C K
Word Address (n)
Device Address
R E A D A C K
Data n
S T O P
L S B R/W DUMMY WRITE
N O * = Don't care bits # = Don't care bit for 24C32A/B A C K
Figure 10. Sequential Read
R E A D A C K S T O P
Device Address SDA Bus Activity
Data Byte n A C K
Data Byte n+1 A C K
Data Byte n+2 A C K
Data Byte n+X
N O R/W A C K
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
IS24C32A/B IS24C64A/B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to +6.25 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA
ISSI
(R)
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE (IS24C64A/B-2 and IS24C32A/B-2)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 1.8V to 5.5V 1.8V to 5.5V
OPERATING RANGE (IS24C64A/B-3 and IS24C32A/B-3)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.5V to 5.5V 2.5V to 5.5V
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
9
IS24C32A/B IS24C64A/B
AC WAVEFORMS Figure 11. Bus Timing
ISSI
tR tF tHIGH tLOW tSU:STO
(R)
SCL
tSU:STA tHD:STA tHD:DAT tSU:DAT tBUF
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
Figure 12. Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK
tWR
STOP Condition START Condition
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
IS24C32A/B IS24C64A/B
DC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC), Industrial (TA = -40oC to +85oC)
Symbol Parameter VOL1 VOL2 VIH VIL ILI ILO Output Low Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VIN = VCC max. Test Conditions VCC = 1.8V, IOL = 0.15 mA VCC = 2.5V, IOL = 3 mA Min. -- -- VCC
X
ISSI
Max. 0.2 0.4 0.7 VCC + 0.5 VCC
X
(R)
Unit V V V V A A
-1.0 -- --
0.3
3 3
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Commercial (TA = 0oC to +70oC), Industrial (TA = -40oC to +85oC)
Symbol Parameter ICC1 ICC2 ISB1 ISB2 ISB3 Vcc Operating Current Vcc Operating Current Standby Current Standby Current Standby Current Test Conditions Read at 400 KHz (Vcc = 5V) Write at 400 KHz (Vcc = 5V) Vcc = 1.8V Vcc = 2.5V Vcc = 5.0 V Min. -- -- -- -- -- Max. 2.0 3.0 1 2 6 Unit mA mA A A A
AC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC) Industrial (TA = -40oC to +85oC)
1.8V-5.5V Symbol Parameter fSCL T tLow tHigh tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT tSU:WP tHD:WP tDH tAA tR tF tWR SCL Clock Frequency Noise Suppression Clock Low Period Clock High Period Bus Free Time Before New Transmission(1) Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data In Setup Time Data In Hold Time WP pin Setup Time WP pin Hold Time Data Out Hold Time (SCL Low to SDA Data Out Change) Clock to Output (SCL Low to SDA Data Out Valid) SCL and SDA Rise Time(1) SCL and SDA Fall Write Cycle Time Time(1) Time(1) Min. Max. 0 -- 4.7 4 4.7 4 4 4 4 100 0 4 4.7 100 100 -- -- -- 100 100 -- -- -- -- -- -- -- -- -- -- -- -- 3500 1000 300 10 2.5V-5.5V Min. Max. 0 -- 1.2 0.6 1.2 0.6 0.6 0.6 0.6 100 0 0.6 1.2 50 50 -- -- -- 400 50 -- -- -- -- -- -- -- -- -- -- -- -- 900 300 300 10 4.5V-5.5V Min. Max. 0 -- 0.6 0.4 0.5 0.25 0.25 0.25 0.25 100 0 0.6 1.2 50 50 -- -- -- 1000 50 -- -- -- -- -- -- -- -- -- -- -- -- 400 300 100 5 Unit KHz ns s s s s s s s ns ns s s ns ns ns ns ms
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
11
IS24C32A/B IS24C64A/B
ISSI
Part Number IS24C32A-2P IS24C32A-2G IS24C32A-2Z IS24C32B-2P IS24C32B-2G IS24C32B-2Z IS24C64A-2P IS24C64A-2G IS24C64A-2Z IS24C64B-2P IS24C64B-2G IS24C64B-2Z IS24C32A-3P IS24C32A-3G IS24C32A-3Z IS24C32B-3P IS24C32B-3G IS24C32B-3Z IS24C64A-3P IS24C64A-3G IS24C64A-3Z IS24C64B-3P IS24C64B-3G IS24C64B-3Z Package 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Voltage Frequency Range 100 KHz 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 2.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V
100 KHz
100 KHz
100 KHz
400 KHz
400 KHz
400 KHz
400 KHz
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
IS24C32A/B IS24C64A/B
ISSI
Part Number IS24C32A-2PI IS24C32A-2GI IS24C32A-2ZI IS24C32B-2PI IS24C32B-2GI IS24C32B-2ZI IS24C64A-2PI IS24C64A-2GI IS24C64A-2ZI IS24C64B-2PI IS24C64B-2GI IS24C64B-2ZI IS24C32A-3PI IS24C32A-3GI IS24C32A-3ZI IS24C32B-3PI IS24C32B-3GI IS24C32B-3ZI IS24C64A-3PI IS24C64A-3GI IS24C64A-3ZI IS24C64B-3PI IS24C64B-3GI IS24C64B-3ZI Package 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP
(R)
ORDERING INFORMATION Industrial Range: -40C to +85C
Voltage Frequency Range 100 KHz 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 2.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V
100 KHz
100 KHz
100 KHz
400 KHz
400 KHz
400 KHz
400 KHz
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00B 05/05/04
13

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